1. Field of the Invention
The present invention relates to an integrated circuit device including a monolithic integrated circuit and a hybrid integrated circuit and, more particularly, to an improvement in a signal wiring structure of an integrated circuit having an ultrahigh-speed performance.
2. Description of the Related Art
A semiconductor device which is used in an optical communication device, a super computer and the like and operates in the GHz band has recently made a rapid development. In particular, the performance of basic elements, e.g. an HBT an HEMT, a GaAs-MESFET, an Si bipolar transistor, and the like has been improved and the performance of an integrated circuit using such an element has been improved accordingly.
The physical size of a conventional integrated circuit chip is as small as about a value between eleven to nineteen mm mainly due to a limitation in manufacturing technique. Substantially no consideration has been made to the length of a signal line, and consideration has been made on only minimization of the wiring capacitance because of the drive capacity. As a result thinning of a signal line as much as the process and the yield permit has generally been performed.
However, such thinning of a signal line to provide a higher operation speed is limited. More specifically, no matter how thin a signal line is made, a capacitance C accompanying a spatial impedance remains, and thus a decrease in capacitance is limited. An increase in series resistance R and a series inductance L (both are inversely proportional to the sectional area of a wire) accompanying the thinning cannot be ignored. As a result, the signal transmission delay caused by these C, R, and L becomes large.
For these reasons, in order to improve the performance of, e.g, an integrated circuit that operates in the GHz band, not only the performance of the elements but also the overall performance of the wiring including signal lines and power source lines must be improved.
In a conventional integrated circuit, signal lines (forward lines) and power source lines (backward lines) are arranged independently of each other in accordance with their applications. Therefore, when such an integrated circuit is operated at an ultrahigh speed, a difference occurs between the "forward transmission time" and the "backward transmission time". No serious problem arose when the element performance was of a level that could ignore this difference. However, as the element performance has been improved recently, this difference cannot be ignored.
This difference causes signal fluctuations during high-speed rising and falling of a signal. Furthermore, since the characteristic impedance and the delay characteristic of a signal line cannot be fixed due to this difference, signal reflection between circuit elements of an integrated circuit or between input and output terminals of a circuit unit cannot be controlled, and delay of a signal due to wiring cannot be quantified, resulting in inconvenience. This makes difficult the circuit simulation indispensable in designing of an ultrahigh-speed integrated circuit.
In this manner, in a conventional integrated circuit, an increase in operating speed and in packing density is sought mainly by increasing the performance of the element or micropatterning the wiring. Substantially no consideration has been made on the signal reflection, high performance of the lines and the like, and an attempt to obtain an ultrahigh operation speed is limited.